In semiconductor manufacturing a lithography tool to supplies radiation that is filtered by a mask to pattern an integrated circuit (IC). In optical lithography, the mask contains a target layout pattern of transparent and opaque areas, which correspond to an individual layer of the IC. The radiation is transmitted by the transparent areas and blocked by the opaque areas, which transfers the target layout pattern onto a substrate to form an on-wafer layout pattern. Some differences between the target layout pattern and on-wafer layout pattern are attributed to parameters of the lithography process, including, but not limited to: beam coherence, depth of focus (DOF), numerical aperture (NA), mask error enhancement factor (MEEF), image log slope (ILS), photoresist thickness, etc. In order to determine how these lithography parameters influence formation of the on-wafer layout pattern, a simulation of the patterning as a function of the lithography parameters is performed.